The present invention relates generally to divider synchronization circuits, and more particularly, to a divider synchronization circuit that is adapted to synchronize the startup of a divider with the reference signal phase in a phase-locked loop.
Conventional programmable divider large scale integrated circuits having integrated phase detectors are commercially available, but none contains a means to synchronize divider startup, or to blank the phase detector output. There is a need to reduce the time required for a phase locked-loop frequency synthesizer to settle to its new frequency and phase when the frequency is changed. In conventional circuits a large phase transient may occur when the divider startup timing is random, and it may initially be as much as 180 degrees out of phase with the reference signal. Consequently, in conventional circuits, a relatively long time must be allowed for the synthesizer output to settle to its final phase. The inventor is not currently aware of any conventional circuit that synchronizes the startup of a divider with the reference signal phase in a phase-locked loop.
Accordingly it would be an improvement in the art to have a divider synchronization circuit that is adapted to synchronize the startup of a divider with the reference signal phase in a phase-locked loop.